FIG. 1A illustrates a prior art spindle motor control with an external sense resistor 110, which in the illustrated embodiment is a FET.
As is illustrated, there is a motor driver integrated circuit (IC) 105 coupled to a spindle motor 115. There is also a motor driver 120 with three individual phases 121-123 each drive the nodes “u,” “v,” and “w,” thereby driving the spindle motor 115.
The amount of current being delivered by the motor driver 120 is sensed by the resistance 110. Generally, a control circuit 125 measures a voltage difference over resistor 110, and therefore knows how much current is being used to drive the spindle motor 115, thereby being able to regulate spindle motor 115.
However, there are drawbacks with this prior art approach. The resistor 110, which can typically be between 0.1 to 0.3 ohms, has to be able to handle a significant amount of current, even an ampere or more, and so is therefore large resistance capable of handling 0.1 to 2 watts or more, which can occupy significant real estate. Moreover, resistances can have significant variability of resistance from manufacturing batch to manufacturing batch; in order to help partially alleviate this drawback, the resistor may present a significant or even prohibitive expense.
Moreover, this approach uses three pins for sensing the three pins are: ICOM, RSNSP, and RSNSN from the motor drive IC. The increase of number of pins means increase in complexity, and possibly, cost.
To clarify, here are some descriptions to the node names:                ICOM is where 3 motor driver FETs are gathered        RSNSP is same node as ICOM, but right above the external resistor or integrated SNS FET (right above drain). The reason node names are different in one node is that, parasitic resistance has to be counted or taken cared. There may some parasitic resistance between ICOM and right above the resistor, which generates some voltage drop. So, in order to monitor ONLY the voltage across the external resistance (or integrated SNS FET), a wire (RSNSP) has to be tapped out and monitor the voltage from right above the resistor (or integrated SNS FET).        RSNSN is same node as GND, but right below the external resistor or integrated SNS FET (right below source). The reason node names are different in one node is that, parasitic resistance has to be counted or taken cared. There may some parasitic resistance between GND and right below the resistor, which generates some voltage drop. So, in order to monitor ONLY the voltage across the external resistance (or integrated SNS FET), a wire (RSNSN) needs to be tapped out and monitor the voltage from right below the resistor (or integrated SNS FET).        
FIG. 1B illustrates a prior art spindle motor driver 133. A motor driver IC 138 includes a power FET driver circuit 150, current sensors 171-173 and FET current sensor transistors 176-178.
Prior Art FIG. 1B is a further evolution of FIG. 1A, which only has only 1 pin output (CS_PIN). This is possibly since the current flowing through the external resistor 180 is smaller than that of 110 in FIG. 1A, so the parasitic resistance is ignorable. This is realized by mirroring and scaling down the current flowing through U, V, and WFETs by using FETs 176, 177, and 178. This enables the value of the external resistor 180 to be ˜kilo ohm order, which is smaller, parasitic resistance insensitive, and cost competitive.
However, there are disadvantages with this circuit as well. Although the resistance 180 is now in the kilohms, and therefore less problematic in some respects due to a lower overall power dissipation than the resistance 110 of the system 100, there are still other drawbacks with this circuit.
In the circuit 150, But this system needs at least 3-sense FET, i.e., Usns 176, Vsns 177, Wsns 178 for each 3-phase FET. However, Usns 176, Vsns 177, Wsns 178 each have their own variation. Therefore, a trimming circuit need for each senses FET 176-178, which therefore complicates the circuit large Moreover, even with trimming, the variation of sense FET 176-178 and the corresponding relative variation (Usns and V-sns or W-sns and Vsns etc.) are still problematic. Generally, due to the inadequate accuracy which comes from process variation, sometimes the control such like an inductive sense or a current limit etc. gets very difficult.
FIG. 1C illustrates a prior art alternative circuit 175 to a use of a sensor resistor. Instead a sensor a current summing FET 182, and a sense FET 184 are employed as a current mirror. However, there are disadvantages with this approach as well. For example, as the sense FET 184 is usually much smaller than the current FET 182, the two FETs can have different gain curves, etc.
As further examples, FIG. 1C The FIG. 1C system 175 requires the current input as the control circuit, while the conventional control system is voltage input. This means, the control system is also required to be re-designed for the current input system. If a resistor is integrated to convert the current to voltage in the IC, there is an extra need of trim for the resistor, in addition to the current trim for FET 182 and 184.
Therefore, there is a need in the art as understood by the present inventors to have a form of spindle control that addresses at least some of the disadvantages of the prior art